1. Field of the Invention
The present invention generally relates to a nonvolatile latch circuit and a system on a chip, and more specifically, to a technology of sensing a change in latch data during an active period in order to store new data in a latch circuit without requiring an additional system booting process in a power-off mode.
2. Description of the Related Art
FIG. 1 is a graph illustrating a current consumption change of a semiconductor chip used by a nanoscale device.
Referring to FIG. 1, when a technology node for representing a design rule of the device is large, active current which is operation current of a system on a chip (hereinafter, referred to as “SOC”) is shown to be much larger than standby current in a non-operation state.
However, as the device size becomes smaller, the active current is shown to increase slowly while the standby current increases rapidly. Consequently, leakage current which is non-switching current on a sub threshold voltage Vt increases more rapidly than the switching current of the active current. That is, the leakage current that penetrates a CMOS is shown to increase rapidly in a standby state where a power source is applied and a chip is not operated.
Therefore, the power consumption of the chip can be reduced by cutting off power supply of the chip in the standby mode. When the power source of the chip is cut off, a circuit for storing and recalling a previous circuit state is required so as to restore the previous circuit state.
FIG. 2 is a circuit diagram illustrating a nonvolatile latch circuit for restoring the previous state in a power-off mode of the chip.
The nonvolatile latch circuit comprises a plurality of inverters IV1-IV8, NMOS transistors N1, N2, and a capacitor unit 10.
An inverter IV1 inverts data D synchronously with respect to a clock CK. A latch R1 which comprises inverter IV2 and IV3 latches an output signal of the inverter IV1 synchronously with respect to a clock /CK. An inverter IV4 inverts an output signal of the latch R1 synchronously with respect to the clock /CK. A latch R2 which comprises inverters IV5 and IV6 latches an output signal of the inverter IV4 to output data Q.
The NMOS transistors N1 and N2 selectively connects the capacitor unit 10 to the latch R1 in response to a switching signal SS. The capacitor unit 10 comprises a plurality of nonvolatile ferroelectric capacitors FC1-FC4. The nonvolatile ferroelectric capacitors FC1 and FC2 are controlled by an output signal of a plate line /PL1 driven by an inverter IV7. The nonvolatile ferroelectric capacitors FC3 and FC4 are controlled by an output signal of a plate line /PL2 driven by an inverter IV8.
The nonvolatile latch circuit positioned in each circuit region of the SOC stores nonvolatile data in a turn-on state of a power supply switch in the power-off mode. That is, through the latches R1 and R2 before the power switch is turned off, data is stored in the capacitor unit 10 or the previous data before the power-on mode is restored.
FIG. 3 is a diagram illustrating a data storage/recall method of the nonvolatile latch circuit.
The nonvolatile latch circuit stores states of the latches R1 and R2 in the capacitor unit 10 during a storage period in entry of the power-off mode, and restores data stored in the latches R1 and R2 during a recall period in entry of the power-on mode.
However, the nonvolatile latch circuit stores the previous data only in the previously power-off mode. As a result, when an accidental power-off state is generated during the active period, latch data in the active state is destroyed so that it is impossible to restore data.